Embedded DRAM Self-Test
Overview
Decreases in process geometries and associated increases in eDRAM densities and sizes are resulting in growing numbers and types of memory defects. Efficient screening and elimination of these defects is critical to achieve acceptable quality and yield levels. An effective eDRAM methodology must, therefore, encompass thorough testing as well as memory repair. LogicVision’s comprehensive eDRAM Self-Test and Repair solution provides all of the critical capabilities necessary for testing and repairing any 3rd party eDRAMs. These capabilities include on-chip memory test algorithm programmability, on-chip self-repair, advanced automation for integrating all on-chip test and repair resources into the design, and automated diagnostic software for real-time interactive eDRAM debug and characterization.
Algorithm Programmability
At design time, one or more user-specified memory test algorithms can be hard-coded into a memory BIST controller. Any of these algorithms can then be selected to be applied to each eDRAM through run-time control. This capability is useful for optimizing test time by selecting shorter test algorithms as the manufacturing process matures. Any BIST controller can also be made to be fully run-time programmable. With this feature implemented, any user specified memory test algorithm can be downloaded into the BIST controller while on the tester. This capability allows any unforeseen defect mechanism to be dealt with, without a design respin. Both the hard and soft programming features can be used within the same BIST controller. In both cases, the specification of virtually any memory test algorithm is supported. A simple-to-use programming language is provided. Tools are also provided for compiling the algorithms and either designing them into the BIST controller or creating the ATE patterns for downloading the algorithm program code into the BIST controller through the TAP within the manufacturing test flow.
Self-Repair
eDRAMs often represent a die’s largest contributor to yield loss due to the very large area and density of these regular circuits. A successful eDRAM strategy must typically incorporate some form of repair methodology in order to achieve profitable yield levels. LogicVision’s embedded memory self-repair solution eliminates the complexities and costs associated with external memory repair flows. This industry leading capability tests and permanently repairs all defective memories in a chip during a single test insertion. The chip-level architecture implementing the self-repair solution is illustrated in Figure 1. The architecture is hierarchical allowing self-test and self-repair capabilities to be added to individual cores as well as at the top level. Central to this architecture is a programmable eFuse Array and associated Fuse Controller.
Electrical or programmable fuses are becoming increasingly popular as they are smaller than laser-based fuses that can be programmed without the need of any external (laser) equipment. Pooling fuses together results in greatly reduced overhead as fuse data is only stored for the memories needing repair on any given die. Managing the storage and retrieval of this fuse data is handled by the Fuse Controller. This controller along with one or more Built-In Self-Test and Repair (BISTR) controllers performs all necessary activities for testing and repairing memories. In this hierarchical architecture, BIST controllers are used for testing memories not containing redundancy. When eDRAMs with redundancy are used, the BIST controller is upgraded to a BISTR controller to not only test the memories, but to also analyze how to repair the faulty ones. This latter capability is typically referred to as Built-In Repair Analysis (BIRA) (see Figure 3). The repair analysis generates fuse data that must be applied to a faulty memory’s repair port to effectuate repair. The fuse data is transferred to serial repair registers that are connected to a chip-wide serial chain controlled by the Fuse Controller. The chain is scanned out by the Fuse Controller, which compresses the incoming fuse data and programs it on-the-fly into the eFuse array. The Fuse Controller is then used at every power-on-reset (POR) event to sequence the fuse data stored in the eFuse Array to all memories needing repair. LogicVision’s self-repair solution works with any 3rd party eDRAMs containing redundancy and with any 3rd party eFuse arrays.
Automated Integration
All on-chip self-test and self-repair capabilities are integrated into the design using LogicVision’s advanced automation flow (see Figure 4). This fully hierarchical flow ensures minimal impact to the design schedule and quick turn-around time. A key aspect of this flow is its ability to automatically create an optimized self-test and repair infrastructure based on the features of the embedded memories (SRAMs and DRAMs), their distribution throughout the chip, user-provided constraints such as maximum test time, and maximum chip power consumption during testing. All design analysis and IP generation and integration can be performed at either RTL or gate level. The LogicVision automation flow has been fully integrated into all major 3rd party physical flows. This integration includes the auto- matic generation of all necessary design constraint files, static timing analysis scripts and formal verification scripts.
Automated Diagnostics
LogicVision Silicon Insight™ product family offers a fully interactive graphical software solution for diagnosing and characterizing eDRAMs tested using LogicVision’s on-chip self-test capabilities.
Failing memory, memory port, and memory I/O information is generated instantaneously at the touch of a button and displayed both graphically as well as sent to a datalog file for future processing. Bit-level failure information can also be generated for any failing memory. The automated solution also provides capabilities for memory performance characterization. Built-in utilities allow measuring memory performance across voltage and/or frequency ranges as well as under various surrounding circuit activity levels. Silicon Insight runs on all major ATE platforms. The software also runs on any Linux platform. In this setup, all communication to the device under test is performed through a simple USB-to-JTAG cable interface that connects to the standard five IEEE 1149.1 pins on any performance board. This provides a convenient desktop bring-up environment that can be made available to every design engineer. This desktop setup also provides optional control of GPIB-based clock generators and power supplies so that these resources can be varied as part of the characteriza- tion or diagnostic activities.