ETSystemMemory
LogicVision’s ETSystemMemory provides a complete solution for the at-speed testing of component memories. The solution provides support for most SRAM and DRAM memories, including those that utilize burst modes of operations, such as DDR and QDR memories.
ETSystemMemory, with its run-time programmable algorithms, provides the flexibility for users to customize the execution of the memory test without relying on the ASIC designer to hard code all of the possible combinations of algorithms into the controller. This greatly reduces the risk that functional memory tests will have to be developed as a result of discovering new defect types not screened with standard test algorithms. In addition to the programmable algorithms, ETSystemMemory accesses and tests the memories at application speed. This allows the memory subsystem to be tested for noise, timing marginality, and power distribution problems. These defects cannot be detected using boundary scan test techniques.
Using the LogicVision TAP, the ETSystemMemory controller can be accessed using the IEEE 1149.1 protocol. The controller can also be accessed and controlled through a processor interface. This access and control flexibility enables the ETSystemMemory controller to be used for initial board debugging, or integrated as part of the board power-on self-test and firmware diagnostics routines.
An automated design kit expedites the generation, integration and verification of the ETSystemMemory controller and interface IP as well as the IEEE 1149.1 TAP and boundary scan logic into an ASIC or SOC design. LogicVision’s design kits are focused on ease-of use, providing high-value to the ASIC designer by automatically generating the embedded test IP elements, assembling the IP elements within the ASIC design, and creating automated test-benches for embedded test verification and vector generation. The ETSystemMemory controller IP and memory test interface IP are available in synthesizable Verilog RTL form.