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ETSerdes - Embedded SerDes Test

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White Paper: Why Use ETSerdes™ to Test High-Speed Serial I/Os?

The explosive adoption of high speed serial data links and the proliferation of multi-lane SerDes channels have created a new set of challenges for semiconductor design and test teams. These multi-Gbps low voltage differential signaling (LVDS) channels are proliferating in many standard forms, including PCI express, Gbit Ethernet, Serial ATA, RapidIO, Fiber Channel and Infiniband to name just a few.

A major issue for these high-speed interface circuits is how one verifies the performance of such interfaces in a low cost manufacturing environment. Bit Error Rate (BER) testing and the use of external test equipment is both very expensive and very complex. Application engineering is a large part of the solution and correlation between channels and systems is extremely difficult. These limitations have lead to wider design and test guard-bands for these devices and in-turn lower yield.

The ETSerdes embedded SerDes loop-back solution from LogicVision structurally characterizes the parameters that determine signal eye distortion tolerance, verifying all the parameters a designer considers during a SerDes core design.

The ultimate level of quality for a SerDes channel is still BER, however BER is directly proportional to the high frequency signal to noise ratio of the channel. The eye parameters shown below are those considered during a SerDes design, and are primarily responsible for BER determination. Structurally verifying these parameters validates the design intent and the manufacturing process.

The unique customer benefits of the ETSerdes solution includes a technology independent implementation, no impact on the SerDes macro performance, at-speed test at wafer and package, all critical parameters verified with sub pico-second accuracy, minimal impact on multi-lane scalability, and reusable IP across multiple devices. Our value proposition also includes device limited test times and a minimal ATE configuration requirements.

ETSerdes is easy to implement and uses the same ETCreate automation suite used in Embedded Memory Test and ETLogic for RTL implementation. It also comes bundled with LogicVision's Silicon Insight package for interactive debug and characterization of the SerDes channel on either the LogicVision Validator, or any LVReady tester.